An electrostatic protection circuit is formed in a semiconductor device to protect an internal circuit from electrostatic discharge (ESD) surge which is applied to the input/output pad. FIG. 1 is a block diagram showing an example of a general configuration of a semiconductor device with an electrostatic protection circuit.
The semiconductor device of FIG. 1 is provided with a power supply (VDD) pad 101, a signal input pad 102, a ground (GND) pad 103, a power supply line 104, a signal line 105, a ground line 106, an input circuit 107, and ESD protection elements 109 and 110. The input circuit 107 is provided with a PMOS transistor P1 and an NMOS transistor N1, and has a function to transfer an external input signal, which is received through the signal line 105 from the signal input pad 102, to an internal circuit through a signal line 108. Each of the ESD protection elements 109 and 110 has a function to discharge the ESD surge inputted to the signal input pad 102 to the power supply line 104 or the ground line 106.
A typical element used as the ESD protection element 109 or 110 is an off transistor. The off transistor is a MOS transistor in which a gate voltage is fixed such that the transistor is set to an off state in an ordinary operation, and it is possible to discharge the ESD surge through a parasitic bipolar operation. When an NMOS transistor is used as the off transistor, the drain of the NMOS transistor is connected with the signal line and a source and gate thereof are connected with the ground line. On the other hand, when a PMOS transistor is used as the off transistor, the drain of the PMOS transistor is connected with the signal line and a gate and source thereof are connected with the power supply line. When the ESD surge is applied to the drain of the off transistor, the off transistor discharges the ESD surge through the parasitic bipolar operation. The off transistor functions effectively as the ESD protection element through such a principle.
However, in the ESD protection element using the parasitic bipolar operation, a design window has become small with the miniaturization of the transistor. FIG. 2 is a graph diagram showing relation of breakdown voltage VBD of a gate insulating film and clamp voltage Vclamp (voltage while discharge is carried out through the parasitic bipolar operation) when the NMOS transistor operates as a parasitic bipolar. The breakdown voltage VBD decreases rapidly with the decrease of film thickness of the gate insulating film, whereas the clamp voltage Vclamp does not fall so much. As a result, a design window of the ESD protection element has become small with reduction of the film thickness of the gate insulating film.
In the electrostatic protection circuit shown in FIG. 1, there is a possibility that when an ESD surge is applied, a voltage VESD of the ESD surge is applied to a protection target circuit just as it, so that the circuit is destroyed. That is, in the electrostatic protection circuit shown in FIG. 1, if the ESD protection elements 109 and 110 do not function sufficiently when the ESD surge is applied, there is a case that a large stress voltage Vstress is applied to the NMOS transistor N1 of the input circuit 107 so that the MOS transistor N1 is destroyed.
As one technique to cope with such a problem, the ESD protection element is provided to carry out discharging in an auxiliary manner so as to relax the applied voltage. The word “auxiliary” means that the ESD surge has smaller discharge ability than the ESD protection element which mainly discharges the ESD surge. In the following description, the ESD protection element which mainly discharges the ESD surge is referred to as a main ESD protection element and the ESD protection element which carries out auxiliary discharge is referred to as a sub ESD protection element. A role of the sub ESD protection element is to form a second discharge route through which a very small part of the discharge current flows, so as to relax a voltage at a critical position, separately from a discharge route which is formed by the main ESD protection element.
FIGS. 3A and 3B are a block diagrams showing configuration examples of a semiconductor device with sub ESD protection elements. In the semiconductor devices shown in FIGS. 3A and 3B, PMOS transistor PP2 and NMOS transistor NN2 are used as the off transistors of the sub ESD protection elements. The PMOS transistor PP2 is provided between a node B on the signal line 105 and the power supply line 104 and the NMOS transistor NN2 is provided between the node B on the signal line 105 and the ground line 106. Moreover, a resistance element R1 is provided between the node B and the signal input pad 102 on the signal line 105. Such a semiconductor device is described in, for example, “ESD in Silicon Integrated Circuits” by Ajith Amerasekera, et al. (John Wiley & Sons Inc (Non-Patent Literature 1) pp. 117-119, FIG. 5.9.
In the semiconductor devices shown in FIGS. 3A and 3B, a discharge route is formed to pass through the resistance element R1 when the ESD surge is applied, and a protection target circuit, especially, the PMOS transistor P1 and the NMOS transistor N1 in the input circuit 107 can be protected by means of a voltage drop of the resistance element R1. In detail, as shown in FIG. 3A, when an ESD surge of a positive polarity to the ground pad 103 is applied to the signal input pad 102 to raise a voltage VESD between the signal line 105 and the ground line 106, a drain junction of the NMOS transistor NN2 breaks down such that the NMOS transistor NN2 carries out a parasitic bipolar operation. Thus, a discharge route is formed to pass from the signal input pad 102 to the ground line 6 through the signal line 105, the resistance element R1 and the NMOS transistor NN2. When discharge current I2nd flows through this discharge route, the voltage drop of I2nd×R1 is generated by the resistance element R1. Thus, a relaxation effect of the stress voltage Vstress which is applied to the NMOS transistor N1 of the input circuit 107 can be obtained.
In the same way, as shown in FIG. 3B, when an ESD surge of the positive polarity to the power supply pad 101 is applied to the signal input pad 102 to raise the voltage VESD between the power supply line 104 and the signal line 105, a discharge route is formed to pass from the signal input pad 102 to the power supply line 4 through the signal line 105, and the resistance element R1 and the parasitic diode element which exists between the drain and the back gate in the PMOS transistor PP2. In such an operation, too, the relaxation effect of the stress voltage Vstress which is applied to the NMOS transistor N1 and the PMOS transistor P1 in the input circuit 7 can be obtained by the voltage drop of the resistance element R1.